The present invention relates to boosting circuits, and more particularly to a boosting circuit which boosts or shifts up a level of a clock signal and derives a boosted clock signal having a voltage higher than a power source voltage.
The power source voltage used for an integrated circuit (IC) was selected at 12 volts, for example. However, there is a recent tendency to lower the power source voltage to 7 volts or 5 volts etc. This tendency is increased by improvements in the performance of transistors, the necessity of matching the levels of transistor-transistor logic (TTL) circuits, etc. In order to speed up the operational speeds of IC memories operated by the lowered voltage, it is necessary to employ a circuit for boosting or shifting up the level of the clock signal.
The conventional boosting circuit connected to a word line driver, for example, comprises a boosting capacitor having one end connected to the word line and the other end is connected to a clock signal. A load capacitor; such as a stray capacitance of the word line driving circuit, is charged up to the power source voltage (V.sub.DD) by an output clock signal from a driver. When the boosting capacitor which has already been charged by the driver, receives the clock signal, the charges of the boosting capacitor are transferred to the load capacitor thereby shifting upward the voltage of the load capacitor.
As will be described hereinafter in conjunction with drawings, the value of the boosted voltage of the load capacitor is determined by the ratio of the capacitances of the boosting and load capacitors. In order to obtain the desired voltage, the larger the capacitance of the load capacitor is, the larger the capacitance of the boosting capacitor should be.
In the conventional circuit, the boosting capacitor is considered to be a load together with the load capacitor for the driver, since the driver charges the boosting capacitor. Accordingly, in a case where the capacitances of the boosting and load capacitors are equal, for example, the driver should drive a total load which is twice as much as the load capacitor above. This results in a voltage waveform that is deformed and rounded, so that the operational speed of the memory becomes slow when the load is the word line driving circuit.